The present invention relates to a logic circuit and a semiconductor device including the logic circuit and, more particularly, to a circuit adapted to a low-power operation.
As an MOS transistor is becoming finer, its breakdown voltage decreases, so that the operation voltage has to be lowered. In this case, in order to maintain high processing speed of the MOS transistor, the threshold voltage of the MOS transistor has to be lowered in accordance with the decrease in the operation voltage for the reason that the operation speed is controlled by an effective gate voltage of the MOS transistor, that is, a value obtained by subtracting the threshold voltage of the MOS transistor from the operation voltage. The larger the value is, the higher the processing speed is. When the threshold voltage is set to about 0.4V or less, however, the MOS transistor cannot be completely turned off due to a subthreshold characteristic (tailing characteristic) of the MOS transistor and a phenomenon occurs such that an undesired direct current flows. Due to such a phenomenon, a substantial direct current of a semiconductor integrated circuit constructed by a number of MOS transistors remarkably increases. Particularly, at the time of high-temperature operation, the threshold voltage of the MOS transistor is low and a tailing factor is high, so that the phenomenon caused by the subthreshold characteristic becomes more serious. In consideration of such circumstances, the applicant herein has proposed a high-speed low-power semiconductor integrated circuit with a finer MOS transistor (Japanese Unexamined Patent Application No. Hei 7(1995)-86916 which corresponds to U.S. Pat. No. 2002/084804). In the semiconductor integrated circuit, control means for controlling a current supply of a large current and a small current is inserted between the source of a MOS transistor and a power source, and the current is supplied to the MOS transistor while switching the currents in accordance with a use, thereby suppressing a subthreshold current which flows in a standby mode (also called xe2x80x9csubthreshold leak currentxe2x80x9d).
The inventor herein has examined the semiconductor integrated circuit (Japanese Unexamined Patent Application No. Hei 7(1995)-86916) proposed by the applicant herein and found that there is room for improvement in the circuit configuration for fixing an output logic.
In the semiconductor integrated circuit proposed by the applicant herein, control means for controlling current supply of a large current and a small current is inserted between a logic circuit having a predetermined function and a power source (VCC, VSS). While switching the current between the large current and the small current by the control means, a current is supplied to the logic circuit. In the case where a path of a current to the logic circuit is interrupted, an output of the logic circuit is held by a level holding circuit. The level holding circuit is formed by connecting two inverters in each of which a p-channel type MOS transistor and an n-channel type MOS transistor are connected in series in a loop shape. The level holding circuit holds an output logic at the time when the current path to the logic circuit is interrupted. Since the holding circuit is formed by connecting two inverters in a loop shape as described above, four MOS transistors are necessary. As a MOS transistor is becoming finer, a number of circuits in which subthreshold current has to be suppressed exist in a semiconductor integrated circuit and, accordingly, a number of holding circuits are necessary. Therefore, the number of MOS transistors even only in the holding circuits is huge.
An object of the present invention is to provide a technique of simplifying a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current.
The above and other objects of the invention and novel features will become apparent from the description of the specification and attached drawings.
An outline of representative ones of inventions disclosed in the specification will be briefly described as follows.
A logic circuit has: an n-channel type first transistor provided between a second power supply terminal and a low-potential-side power and capable of interrupting power supply to the logic gate in accordance with an input control signal; and a p-channel type second transistor provided between a high-potential-side power and an output node of the logic gate and capable of fixing the output node of the logic gate to the high level interlockingly with the power supply interrupting operation of the first transistor, and a threshold voltage of the first transistor is set to be higher than that of the transistor as a component of the logic gate. As a MOS transistor is becoming finer, its breakdown voltage decreases, so that the operation voltage has to be lowered. In order to maintain high-speed switching operation of a transistor, the threshold voltage of the transistor has to be decreased in accordance with the decrease in the operation voltage.
According to the means, the first transistor interrupts the power supply to the logic gate and the second transistor fixes the output node of the logic gate to the high level interlockingly with the power supply interrupting operation. Consequently, a circuit for fixing the output logic of the logic gate while suppressing the subthreshold current is constructed by the first and second transistors, thereby achieving simplification of the circuit. In this case, by setting the threshold voltage of the first transistor to be higher than that of the transistor as a component of the logic gate, reduction in the subthreshold current in the first transistor is assured.
A logic circuit includes: an n-channel type first transistor provided between a second power supply terminal and a low-potential-side power and capable of interrupting power supply to a logic gate in accordance with an input control signal; and an n-channel type second transistor provided between the low-potential-side power and an output node of the logic gate and capable of fixing the output node of the logic gate to the low level interlockingly with the power supply interrupting operation of the first transistor, and a threshold voltage of the first transistor is set to be higher than that of the transistor as a component of the logic gate.
According to the means, the first transistor interrupts the power supply to the logic gate and the second transistor fixes the output node of the logic gate to the high level interlockingly with the power supply interrupting operation. Consequently, a circuit for fixing the output logic of the logic gate while suppressing the subthreshold current is constructed by the first and second transistors, thereby achieving simplification of the circuit. In this case, by setting the threshold voltage of the first transistor to be higher than that of the transistor as a component of the logic gate, reduction in the subthreshold current in the first transistor is assured.